Update STM32F446 default HSE to 8MHz (#25717)

keyboards/handwired/onekey/nucleo_f446re/board.h

@@ -4,6 +4,5 @@
 
 #include_next <board.h>
 
-#undef STM32_HSECLK
-#define STM32_HSECLK 8000000U
+// Configure clocks to use onboard STLINKs MCO as HSE is not populated by default
 #define STM32_HSE_BYPASS

keyboards/handwired/onekey/nucleo_f446re/mcuconf.h

@@ -4,12 +4,6 @@
 
 #include_next <mcuconf.h>
 
-#undef STM32_PLLM_VALUE
-#define STM32_PLLM_VALUE 4
-
-#undef STM32_PLLSAIM_VALUE
-#define STM32_PLLSAIM_VALUE 4
-
 #undef STM32_ADC_USE_ADC1
 #define STM32_ADC_USE_ADC1 TRUE
 

keyboards/handwired/onekey/nucleo_f446re/readme.md

@@ -1,4 +1,4 @@
-# STM32 Nucleo-L432 onekey
+# STM32 Nucleo-F446 onekey
 
 To trigger keypress, short together pins *A0* and *A1*. Note that the pin numbering is relative to the MCU, so that A0 and A1 refer to PA0 and PA1 on the MCU (which are also labelled A0 and A1 on the board, but this isn't true for the other PAx pins). 
 

keyboards/ibm/model_m_4th_gen/overnumpad_1xb/mcuconf.h

@@ -0,0 +1,11 @@
+// Copyright 2025 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+#include_next <mcuconf.h>
+
+#undef STM32_PLLM_VALUE
+#define STM32_PLLM_VALUE 8
+
+#undef STM32_PLLSAIM_VALUE
+#define STM32_PLLSAIM_VALUE 8

keyboards/unicomp/classic_ultracl_post_2013/overnumpad_1xb/mcuconf.h

@@ -0,0 +1,11 @@
+// Copyright 2025 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+#include_next <mcuconf.h>
+
+#undef STM32_PLLM_VALUE
+#define STM32_PLLM_VALUE 8
+
+#undef STM32_PLLSAIM_VALUE
+#define STM32_PLLSAIM_VALUE 8

keyboards/unicomp/classic_ultracl_pre_2013/overnumpad_1xb/mcuconf.h

@@ -0,0 +1,11 @@
+// Copyright 2025 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+#include_next <mcuconf.h>
+
+#undef STM32_PLLM_VALUE
+#define STM32_PLLM_VALUE 8
+
+#undef STM32_PLLSAIM_VALUE
+#define STM32_PLLSAIM_VALUE 8

keyboards/unicomp/pc122/overnumpad_1xb/mcuconf.h

@@ -0,0 +1,11 @@
+// Copyright 2025 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+#include_next <mcuconf.h>
+
+#undef STM32_PLLM_VALUE
+#define STM32_PLLM_VALUE 8
+
+#undef STM32_PLLSAIM_VALUE
+#define STM32_PLLSAIM_VALUE 8

keyboards/unicomp/spacesaver_m_post_2013/overnumpad_1xb/mcuconf.h

@@ -0,0 +1,11 @@
+// Copyright 2025 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+#include_next <mcuconf.h>
+
+#undef STM32_PLLM_VALUE
+#define STM32_PLLM_VALUE 8
+
+#undef STM32_PLLSAIM_VALUE
+#define STM32_PLLSAIM_VALUE 8

keyboards/unicomp/spacesaver_m_pre_2013/overnumpad_1xb/mcuconf.h

@@ -0,0 +1,11 @@
+// Copyright 2025 QMK
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+#include_next <mcuconf.h>
+
+#undef STM32_PLLM_VALUE
+#define STM32_PLLM_VALUE 8
+
+#undef STM32_PLLSAIM_VALUE
+#define STM32_PLLSAIM_VALUE 8

platforms/chibios/boards/GENERIC_STM32_F446XE/configs/board.h

@@ -15,7 +15,6 @@
  */
 #pragma once
 
-#define STM32_HSECLK 16000000
 // The following is required to disable the pull-down on PA9, when PA9 is used for the keyboard matrix:
 #define BOARD_OTG_NOVBUSSENS
 

platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h

@@ -13,6 +13,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
+#pragma once
 
 #ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
 #    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE

platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h

@@ -48,7 +48,7 @@
 #define STM32_CLOCK48_REQUIRED              TRUE
 #define STM32_SW                            STM32_SW_PLL
 #define STM32_PLLSRC                        STM32_PLLSRC_HSE
-#define STM32_PLLM_VALUE                    8
+#define STM32_PLLM_VALUE                    4
 #define STM32_PLLN_VALUE                    180
 #define STM32_PLLP_VALUE                    2
 #define STM32_PLLQ_VALUE                    7
@@ -58,7 +58,7 @@
 #define STM32_PLLI2SP_VALUE                 4
 #define STM32_PLLI2SQ_VALUE                 4
 #define STM32_PLLSAIN_VALUE                 192
-#define STM32_PLLSAIM_VALUE                 8
+#define STM32_PLLSAIM_VALUE                 4
 #define STM32_PLLSAIP_VALUE                 8
 #define STM32_PLLSAIQ_VALUE                 4
 #define STM32_HPRE                          STM32_HPRE_DIV1